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400 khz 2-wire serial e 2 prom 128k 16k x 8 bit xicor, 1995, 1996 patents pending characteristics subject to change without notice 900-5004.7 3/5/99 sh 1 X24129 functional diagram features 1.8v to 3.6v, 2.5v to 5.5v and 4.5v to 5.5v power supply operation low power cmos ?ctive read current less than 1ma ?ctive write current less than 3ma ?tandby current less than 1 m a 400khz fast mode 2-wire serial interface ?own to 1.8v ?chmitt trigger input noise suppression ?utput slope control for ground bounce noise elimination internally organized 16k x 8 32 byte page write mode ?inimizes total write time per byte hardware write protect bidirectional data transfer protocol self-timed write cycle ?ypical write cycle time of 5ms high reliability ?ndurance: 1,000,000 cycles ?ata retention: 100 years 16-lead soic description the X24129 is a cmos serial e 2 prom memory, internally organized 16k x 8. the device features a serial interface and software protocol allowing opera- tion on a simple two wire bus. the bus operates at 400khz all the way down to 1.8v. three device select inputs (s 0 ? 2 ) allow up to eight devices to share a common two wire bus. hardware write protection is provided through a write protect (wp) input pin on the X24129. when the wp pin is high, the upper quadrant of the serial e 2 prom array is protected against any nonvolatile write attempts. xicor serial e 2 prom memories are designed and tested for applications requiring extended endurance. inherent data retention is greater than 100 years. serial e 2 prom data and address (sda) scl s2 s1 s0 wp command decode and control logic device select logic write protect logic page decode logic data register y decode logic e 2 prom write voltage control 7041 fm 01 array 16k x 8
X24129 2 pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may be wire-ored with any number of open drain or open collector outputs. an open drain output requires the use of a pull-up resistor. for selecting typical values, refer to the pull- up resistor selection graph at the end of this data sheet. device select (s 0 , s 1 , s 2 ) the device select inputs (s 0 , s 1 , s 2 ) are used to set the ?st three bits of the 8-bit slave address. this allows up to eight devices to share a common bus. these inputs can be static or actively driven. if used statically they must be tied to v ss or v cc as appro- priate. if actively driven, they must be driven with cmos levels. write protect (wp) the write protect input controls the hardware write protect feature. when held low, hardware write protection is disabled and the device can be written normally. when this input is held high, write protec- tion is enabled, and nonvolatile writes are disabled to the upper quadrant of the e 2 prom array. pin names 7041 frm t01 pin configuration symbol description s 0 , s 1 , s 2 device select inputs sda serial data scl serial clock wp write protect v ss ground v cc supply voltage X24129 16-lead soic 7041 fm 02 v cc wp scl s 0 s 1 nc 1 2 3 4 7 6 5 v ss sda nc nc nc nc nc s 2 .244 .394 9 10 11 12 13 14 nc 8 16 15 nc
X24129 3 device operation the device supports a bidirectional, bus oriented protocol. the protocol de?es any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master will always initiate data trans- fers, and provide the clock for both transmit and receive operations. therefore, the device will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. refer to figures 1 and 2. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. scl sda data stable data change 7041 fm 03 scl sda start bit stop bit 7041 fm 04 figure 1. data validity figure 2. definition of start and stop
X24129 4 figure 3. acknowledge response from receiver stop condition all communications must be terminated by a stop condition, which is a low to high transition of sda when scl is high. the stop condition is also used to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus. acknowledge acknowledge is a software convention used to indicate successful data transfer. the transmitting device, either master or slave, will release the bus after trans- mitting eight bits. during the ninth clock cycle the receiver will pull the sda line low to acknowledge that it received the eight bits of data. refer to figure 3. the device will respond with an acknowledge after recognition of a start condition and its slave address. if both the device and a write operation have been selected, the device will respond with an acknowledge after the receipt of each subsequent byte. in the read mode the device will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. if an acknowledge is not detected, the device will terminate further data trans- missions. the master must then issue a stop condition to return the device to the standby power mode and place the device into a known state. scl from master data output from transmitter 1 89 data output from receiver start acknowledge 7041 fm 05
X24129 5 figure 4. device addressing 1 s 1 s 0 r/w device select 010s 2 device type identifier slave address byte d7 d2 d1 d6 d5 d4 d3 data byte a2 a1 a0 a5 low order address a4 a3 address byte 0 0 a10 a9 a8 0 high order address a11 address byte 1 a13 a7 a6 d0 7041 fm 06 a12 device addressing following a start condition, the master must output the address of the slave it is accessing. the ?st four bits of the slave address byte are the device type identi?r bits. these must equal ?010? the next 3 bits are the device select bits s 0 , s 1 , and s 2 . this allows up to 8 devices to share a single bus. these bits are compared to the s 0 , s 1 , and s 2 device select input pins. the last bit of the slave address byte de?es the operation to be performed. when the r/w bit is a one, then a read operation is selected. when it is zero then a write operation is selected. refer to ?ure 4. after loading the slave address byte from the sda bus, the device compares the device type bits with the value ?010 and the device select bits with the status of the device select input pins. if the compare is not successful, no acknowledge is output during the ninth clock cycle and the device returns to the standby mode. the byte address is either supplied by the master or obtained from an internal counter, depending on the operation. when required, the master must supply the two address bytes as shown in ?ure 4. the internal organization of the e 2 prom array is 512 pages by 32 bytes per page. the page address is partially contained in the address byte 1 and partially in bits 7 through 5 of the address byte 0. the speci? byte address is contained in bits 4 through 0 of the address byte 0. refer to ?ure 4.
X24129 6 figure 5. page write sequence write operations byte write for a byte write operation, the device requires the slave address byte, the word address byte 1, and the word address byte 0, which gives the master access to any one of the bytes in the array. upon receipt of the word address byte 0, the device responds with an acknowledge, and waits for the ?st eight bits of data. after receiving the 8 bits of the data byte, the device again responds with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile memory. while the internal write cycle is in progress the device inputs are disabled and the device will not respond to any requests from the master. the sda pin is at high impedance. see ?ure 4. page write operation the device executes a thirty-two byte page write operation. for a page write operation, the device requires the slave address byte, address byte 1, and address byte 0. address byte 0 must contain the ?st byte of the page to be written. upon receipt of address byte 0, the device responds with an acknowledge, and waits for the ?st eight bits of data. after receiving the 8 bits of the ?st data byte, the device again responds with an acknowledge. the device will respond with an acknowledge after the receipt of each of 31 more bytes. each time the byte address is internally incre- mented by one, while page address remains constant. when the counter reaches the end of the page, the master terminates the data loading by issuing a stop condition, which causes the device to begin the nonvolatile write cycle. all inputs are disabled until completion of the nonvolatile write cycle. the sda pin is at high impedance. refer to ?ure 5 for the address, acknowledge, and data transfer sequence. s t a r t slave address s t o p a c k a c k a c k a c k a c k 7012 ill f08.1 data (1) signals from the master sda bus signals from the slave data (32) address byte 1 address byte 0 1 0 1 0 0 s p signals from the master sda bus signals from the slave s t a r t slave address s t o p a c k a c k a c k a c k word address byte 1 data 1 0 1 0 0 word address byte 0 s p 7041 fm 07 signals from the master sda bus signals from the slave s t a r t slave address s t o p a c k a c k a c k a c k word address byte 1 data 1 0 1 0 0 word address byte 0 s p 7041 fm 07 figure 4. byte write sequence
X24129 7 acknowledge polling the maximum write cycle time can be signi?antly reduced using acknowledge polling. to initiate acknowledge polling, the master issues a start condi- tion followed by the slave address byte for a write or read operation. if the device is still busy with the nonvolatile write cycle, then no ack will be returned. if the device has completed the nonvolatile write opera- tion, an ack will be returned and the host can then proceed with the read or write operation. refer to ?ure 6. byte load completed by issuing stop. enter ack polling issue start issue slave address byte (read or program) ack returned? nonvolatile write cycle complete. continue sequence? continue normal read or program command sequence proceed issue stop no yes yes issue stop no 7041 fm 09 read operations read operations are initiated in the same manner as write operations with the exception that the r/w bit of the slave address byte is set to one. there are three basic read operations: current address reads, random reads, and sequential reads. current address read internally, the device contains an address counter that maintains the address of the last byte read or written, incremented by one. after a read operation from the last address in the array, the counter will ?oll over to the ?st address in the array. after a write operation to the last address in a given page, the counter will ?oll over to the ?st address of the same page. upon receipt of the slave address byte with the r/w bit set to one, the device issues an acknowledge and then transmits the byte at the current address. the master terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition. refer to ?ure 7 for the address, acknowledge, and data transfer sequence. it should be noted that the ninth clock cycle of the read operation is not a ?on? care. to terminate a read operation, the master must either issue a stop condi- tion during the ninth cycle or hold sda high during the ninth clock cycle and then issue a stop condition. from the s t a r t slave address s t o p a c k data signals from the master sda bus signals slave 1 sp 010 1 7041 fm 10 figure 6. acknowledge polling sequence figure 7. current address read sequence
X24129 8 random read random read operation allows the master to access any memory location in the array. prior to issuing the slave address byte with the r/w bit set to one, the master must ?st perform a ?ummy write operation. the master issues the start condition and the slave address byte with the r/w bit low, receives an acknowledge, then issues address byte 1, receives another acknowledge, then issues address byte 0 containing the address of the byte to be read. after the device acknowledges receipt of address byte 0, the master issues another start condition and the slave address byte with the r/w bit set to one. this is followed by an acknowledge and then eight bits of data from the device. the master terminates the read oper- ation by not responding with an acknowledge and then issuing a stop condition. refer to ?ure 8 for the address, acknowledge, and data transfer sequence. the device will perform a similar operation called ?et current address if a stop is issued instead of the second start shown in ?ure 9. the device will go into standby mode after the stop and all bus activity will be ignored until a start is detected. the effect of this oper- ation is that the new address is loaded into the address counter, but no data is output by the device. the next current address read operation will read from the newly loaded address. sequential read sequential reads can be initiated as either a current address read or random read. the ?st byte is trans- mitted as with the other modes; however, the master now responds with an acknowledge, indicating it requires additional data. the device continues to output data for each acknowledge received. the master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. the data output is sequential, with the data from address n followed by the data from address n + 1. the address counter for read operations increments through all byte addresses, allowing the entire memory contents to be read during one operation. at the end of the address space the counter ?olls over to address 0000h and the device continues to output data for each acknowledge received. refer to ?ure 9 for the acknowledge and data transfer sequence. slave address s s t o p a c k a c k a c k a c k data (1) data (2) signals from the master sda bus signals from the slave data (n?) data (n) 1 p 7041 fm 12 signals from the master sda bus signals from the slave s t a r t slave address s t o p a c k a c k a c k address byte 1 slave address 0 address byte 0 s t a r t 1 data a c k s p s 1010 7041 fm 11 figure 8. random read sequence figure 9. sequential read sequence
X24129 9 absolute maximum ratings* temperature under bias X24129 .......................................?5 c to +135 c storage temperature ........................?5 c to +150 c voltage on any pin with respect to v ss .................................... ?v to +7v d.c. output current ..............................................5ma lead temperature (soldering, 10 seconds) .............................. 300 c *comment stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. d.c. operating characteristics 7041 frm t06.1 capacitance t a = +25 c, f = 1mhz, v cc = 5v 7041 frm t07 notes: (1) must perform a stop command prior to measurement. (2) v il min. and v ih max. are for reference only and are not 100% tested. (3) this parameter is periodically sampled and not 100% tested. limits symbol parameter min. max. units test conditions i cc1 v cc supply current (read) 1 ma scl = v cc x 0.1/v cc x 0.9 levels @ 400khz, sda = open, all other inputs = v ss or v cc ?0.3v i cc2 v cc supply current (write) 3ma i sb1 (1) v cc standby current 3 m a scl = sda = v cc ?0.3v, all other inputs = v ss or v cc ?0.3v, v cc = 5v 10% i sb2 (1) v cc standby current 1 m a scl = sda = v cc ?0.1v, all other inputs = v ss or v cc ?0.1v, v cc = 1.8v i li input leakage current 10 m av in = v ss to v cc i lo output leakage current 10 m av out = v ss to v cc v ll (2) input low voltage ?.5 v cc x 0.3 v v ih (2) input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 3ma v hys (3) hysteresis of schmitt trigger inputs v cc x 0.05 v symbol parameter max. units test conditions c i/o (3) input/output capacitance (sda) 8 pf v i/o = 0v c in (3) input capacitance (s 0 , s 1 , s 2 , scl,wp) 6 pf v in = 0v recommended operating conditions 7041 frm t04 temperature min. max. commercial 0 c +70 c industrial ?0 c +85 c 7041 frm t05 supply voltage limits X24129 4.5v to 5.5v X24129?.5 2.5v to 5.5v X24129?.8 1.8v to 3.6v
X24129 10 a.c. operating characteristics (over the recommended operating conditions, unless otherwise specified.) read & program cycle limits 7041 frm t09 power-up timing (4) 7041 frm t10 notes: (4) t pur and t puw are the delays required from the time v cc is stable until the speci?d operation can be initiated. these parameters are periodically sampled and not 100% tested. (5) c b = total capacitance of one bus line in pf (6) t aa = 1.1? max below v cc = 2.5v. symbol parameter min. max. units f scl scl clock frequency 0 400 khz t i noise suppression time constant at scl, sda inputs 50 ns t aa (6) scl low to sda data out valid 0.1 0.9 m s t buf time the bus must be free before a new transmission can start 1.2 m s t hd:sta start condition hold time 0.6 m s t low clock low period 1.2 m s t high clock high period 0.6 m s t su:sta start condition setup time (for a repeated start condition) 0.6 m s t hd:dat data in hold time 0 m s t su:dat data in setup time 100 ns t r sda and scl rise time 20+0.1xc b (5) 300 ns t f sda and scl fall time 20+0.1xc b (5) 300 ns t su:sto stop condition setup time 0.6 m s t dh data out hold time 50 ns t of output fall time 20 + 0.1c b (5) 250 ns symbol parameter max. units t pur power-up to read operation 1 ms t puw power-up to write operation 5 ms a.c. conditions of test 7041 frm t08 input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 equivalent a.c. load circuit 5v 1.53k w 100pf output 7041 fm 13
X24129 11 symbol table waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance 7041 fm 17 the program cycle time is the time from a valid stop condition of a program sequence to the end of the internal erase/program cycle. during the program cycle, the X24129 bus interface circuits are disabled, sda is allowed to remain high, and the device does not respond to its slave address. bus timing t su:sta t hd:sta t hd:dat t su:dat t low t su:sto t r t buf scl sda in sda out t dh t aa t f t high 7041 fm 14 program cycle limits 7041 frm t11 symbol parameter min. typ. (7) max. units t wr (8) program cycle time 5 10 ms scl sda 8th bit word n ack t wr stop condition start condition 7041 fm 15 guidelines for calculating typical values of bus pull-up resistors 120 100 80 40 60 20 20 40 60 80 100 120 0 0 resistance (k w ) bus capacitance (pf) min. resistance max. resistance r max = c bus t r r min = i ol min v cc max =1.8k w 7041 fm 16 bus timing notes: (7) typical values are for t a = 25 c and nominal supply voltage (5v). (8) t wr is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. it is the maximum time the device requires to automatically complete the nonvolatile write operation.
X24129 12 packaging information 7041 fm 19 16-lead plastic small outline gull wing package type s 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.020 (0.51) pin 1 pin 1 index 0.050 (1.27) 0.386 (9.80) 0.394 (10.01) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 note: all dimensions in inches (in parentheses in millimeters) 0.250" 0.050" typical 0.030" typical 16 places footprint 0.010 (0.25) 0.020 (0.50) 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 ?8 x 45 0.050" typical
X24129 13 ordering information part mark convention device X24129 x x -x X24129 x x limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the f reedom of the described devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue production and change speci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, licenses are implied. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874 , 967; 4,883, 976. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. xicor's products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) su pport or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. v cc range blank = 5v 10% 2.5 = 2.5v to 5.5v temperature range blank = 0 c to +70 c i = ?0 c to +85 c package X24129 s = 16-lead soic blank = 4.5v to 5.5v, 0 c to +70 c i = 4.5v to 5.5v, ?0 c to +85 c ae = 2.5v to 5.5v, 0 c to +70 c af = 2.5v to 5.5v, ?0 c to +85 c s= 16-lead soic 1.8 = 1.8v to 3.6v ag = 1.8v to 3.6v, 0? to +70? ah = 1.8v to 3.6v, ?0? to +85?

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